1. Field of the Invention
The present invention relates to a semiconductor device and more specifically to a semiconductor device ensuring the planarity of an interlayer insulating film and preventing displacement of an interconnection thereby achieving a high degree of integration.
2. Description of the Background Art
As one example of conventional semiconductor devices, a semiconductor device including an MOS transistor will be described with reference to the drawings. Referring to FIG. 47, a plurality of gate electrode portions 55 including a polycrystalline silicon film 55a, a tungsten silicide film 55b and a silicon oxide film 55c are formed on the surface of a silicon semiconductor substrate 51 with a gate insulating film 54 interposed therebetween. A pair of impurity diffusion layers 56a, 56b are formed at the surface of silicon semiconductor substrate 51 with one gate electrode portion 55 sandwiched therebetween. A pair of impurity diffusion layers 56c, 56d are formed at the surface of silicon semiconductor substrate 51 with another gate electrode portion 55 sandwiched therebetween. A sidewall insulating film 57 is formed on the both side surfaces of gate electrode portion 55. Gate electrode portion 55 and a pair of impurity diffusion layers 56a, 56b constitute one MOS transistor. Further, gate electrode portion 55 and a pair of impurity diffusion layers 56c, 56d constitute another MOS transistor. Gate electrode portion 55 of each MOS transistor serves as a first interconnection layer. MOS transistors are electrically insulated from one another by a separating oxide film 53 that is formed in an element separating trench 52 at the surface of silicon semiconductor substrate 51.
A silicon oxide film 58 is formed on silicon semiconductor substrate 51 to cover gate electrode portion 55. On silicon oxide film 58, a silicon oxide film doped with boron and phosphorous, that is, a BPSG (Boro-Phospho-Silicate-Glass) film 59 is formed. A silicon oxide film 60 is formed on BPSG film 59. A plurality of second interconnection layers 62 including a polycrystalline silicon film 62a, a tungsten silicide film 62b and a silicon oxide film 62c are formed on silicon oxide film 60. One second interconnection layer 62 is electrically connected to gate electrode portion 55 as a first interconnection layer by a polycrystalline silicon film filled in contact hole 61a that is formed in BPSG film 59 and silicon oxide films 60, 58. Another second interconnection layer 62 is electrically connected to impurity diffusion layer 56b by a polycrystalline silicon film filled in a contact hole 61b that is formed in BPSG film 59 and silicon oxide films 60, 58. A silicon oxide film 63 is formed on silicon oxide film 60 to cover second interconnection layer 62. A BPSG film 64 is also formed on silicon oxide film 63. A plurality of third interconnection layers 67 are formed on BPSG film 64.
Third interconnection layers 67 are electrically connected to gate electrode portion 55 and impurity diffusion layers 56c, 56d by plugs 66a, 66b, 66c e.g. of tungsten filled in contact holes 65a, 65b, 65c that are formed in BPSG films 59, 64 and silicon oxide films 63, 60, 58. Third interconnection layer 67 is also electrically connected to second interconnection layer 62 by a plug 66d filled in a contact hole 65d that is formed in BPSG film 64 and silicon oxide film 63. The conventional semiconductor device has such a configuration.
One example of the method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to FIG. 48, element separating trench 52 is formed at the surface of silicon semiconductor substrate 51 by prescribed photolithography and RIE (Reactive Ion Etching) methods. To fill element separating trench 52, a silicon oxide film (not shown) having a film thickness of approximately 300 to 800 nm is then formed on silicon semiconductor substrate 51 by the CVD method. The silicon oxide film is polished by the CMP (Chemical Mechanical Polishing) method to form separating oxide film 53 in element separating trench 52. Gate oxide film 54 having a film thickness of 5 to 15 nm is then formed on the surface of silicon semiconductor substrate 51 by the thermal oxidation method. On gate oxide film 54, a polycrystalline silicon film containing phosphorous or arsenic, a tungsten silicide film and a silicon oxide film (they are not shown) are formed. A plurality of gate electrode portions 55 as the first interconnection layers including polycrystalline silicon film 55a, tungsten silicide film 55b and silicon oxide film 55c are formed by the prescribed photolithography and RIE methods. By implanting an impurity of a prescribed conductive type into silicon semiconductor substrate 51 using gate electrode portion 55 as a mask, a region (not shown) of a comparatively low impurity concentration is formed.
To cover gate electrode portion 55, a silicon oxide film (not shown) having a film thickness of approximately 10 to 50 nm is then formed on silicon semiconductor substrate 51 by the CVD method. The silicon oxide film is etched by the RIE method to form sidewall insulating film 57 on the both side surfaces of gate electrode portion 55. By implanting an impurity of a prescribed conductive type into silicon semiconductor substrate 51 using sidewall insulating film 57 and gate electrode portion 55 as a mask, a region (not shown) of a comparatively high impurity concentration is formed. Thus, a pair of impurity diffusion layers 56a, 56b and a pair of impurity diffusion layers 56c, 56d are respectively formed at the surface of silicon semiconductor substrate 51 with gate electrode potions 55 sandwiched therebetween. Thereafter, comparatively thin silicon oxide film 58 is formed on silicon semiconductor substrate 51 by the CVD method to cover gate electrode portion 55. BPSG film 59 is formed on silicon oxide film 58 by the CVD method.
Referring to FIG. 49, BPSG film 59 is heated at a temperature of approximately 850xc2x0 C. to locally planarize the surface of BPSG film 59. In other words, BPSG film 59 is reflowed. Locally planarizeed BPSG film 59 is etched by the RIE method or a hydrofluoric acid solution to make BPSG film 59 thinner.
Referring to FIG. 50, comparatively thin silicon oxide film 60 is formed on BPSG film 59 by the CVD method. Then, contact hole 61a exposing the surface of tungsten silicide film 55b of gate electrode portion 55 and contact hole 61b exposing the surface of impurity diffusion layer 56b are formed in BPSG film 59 and silicon oxide films 60, 58 by the prescribed photolithography and RIE methods. A polycrystalline silicon film, a tungsten silicide film and a silicon oxide film (they are not shown) are then formed on silicon oxide film 60 by the CVD method. Second interconnection layer 62 including polycrystalline silicon film 62a, tungsten silicide film 62b and silicon oxide film 62c is then formed by the prescribed photolithography and RIE methods.
Referring to FIG. 51, comparatively thin silicon oxide film 63 is formed on silicon oxide film 60 by the CVD method to cover second interconnection layer 62. BPSG film 64 is then formed on silicon oxide film 63 by the CVD method.
Referring to FIG. 52, BPSG film 64 is heated at a temperature of approximately 800xc2x0 C. to locally planarize the surface of BPSG film 64. Thereafter, BPSG film 64 is etched by the RIE method or a hydrofluoric acid solution, if necessary, to further planarize the surface of BPSG film 64.
Referring to FIG. 53, contact hole 65a exposing the surface of tungsten silicide film 55b of gate electrode portion 55, contact holes 65b, 65c exposing the surfaces of impurity diffusion layers 56c, 56d, and contact hole 65d exposing the surface of tungsten silicide film 62b of second interconnection layer 62 are formed in BPSG film 64 by the prescribed photolithography and RIE methods. Thereafter, an impurity of a prescribed conductive type is implanted in contact holes 65a, 65b, 65c, 65d. The impurity is activated by heating at a temperature of 750xc2x0 C. lower than the heating temperature for locally planaiizing BPSG film 64.
Then, a tungsten thin film (not shown) is formed on BPSG film 64 by the CVD method using WF6, for example, as a material. The tungsten thin film is etched by the RIE method to form tungsten plugs (not shown) in contact holes 65a, 65b, 65c, 65d. An aluminum copper alloy film (not shown) is formed on BPSG film 64 by the sputtering method. Then, the third interconnection layers electrically connected to gate electrode portion 55, impurity diffusion layers 56c, 56d and the like are formed by the prescribed photolithography and RIE methods to complete the semiconductor device shown in FIG. 47. The conventional semiconductor device is manufactured as described above.
As LSIs miniaturize in recent, years, processing of contact holes 61a, 61b, 65a to 65d, second interconnection layer 62 and third interconnection layer 67 with high dimensional precision is becoming difficult. Especially, in order to ensure prescribed dimensional precision in a lateral direction, the NA value (Numerical Aperture) of a lens used for an exposing device is set at a higher value to improve resolution in photolithography. When the planarity of a film surface to be applied with a resist is poor, however, halation makes it difficult to form a pattern that is highly dimensionally precise. Since the NA value of a lens is set at a higher value, it is difficult to ensure the depth of focus. In filling polycrystalline silicon, tungsten or the like in contact holes 61a, 61b, 65a to 65d that are formed in BPSG films 59, 64 and the like, the polycrystalline silicon or tungsten may be left without being etched at the step portions of BPSG films 59, 64. Therefore, more planarized surface shapes are required for BPSG film 59 serving as the base of second interconnection layer 62 and BPSG film 64 serving as the base of third interconnection layer 67.
Here, the step portions of the BPSG films are locally planarized by heating. The degree of planarization depends on the concentration of boron and phosphorous contained in the BPSG films, the heating temperature and the like, and the BPSG films are locally planarized to a greater extent as the concentration of boron and phosphorous is higher or as the temperature is higher.
When the concentration of boron and phosphorous in lower layer BPSG film 59 is made almost the same as the concentration of boron and phosphorous in upper layer BPSG film 64 so as to ensure the planarity of the base of second interconnection layer 62, lower layer BPSG film 59 is also reflowed and transformed in heating upper layer BPSG film 64. Therefore, second interconnection layer 62 formed on BPSG film 59 might be displaced as BPSG film 59 is transformed. Thus, second interconnection layer 62, for example, might come into contact with tungsten plug 66b, causing an electrical short.
In order to suppress such displacement of second interconnection layer 62, the displacement can be suppressed to approximately 1 xcexcm by setting lower the heating temperature for upper layer BPSG film 64. In order to cope with the requirement for the heating at a lower temperature as LSIs are miniaturized, however, the lower temperature of the heating for the upper layer BPSG film is approaching a limit. As the LSIs are further miniaturized, suppressing displacement of second interconnection layer 62 to approximately 0.1 xcexcm is required. Therefore, simultaneously ensuring the planarity of the base of the second interconnection layer and the like and preventing displacement of the second interconnection layer are expected to be extremely difficult in the conventional semiconductor device. As a result, easy miniaturization of LSIs is expected to be difficult.
The present invention aims at solving the expected problems above and its object is to provide a semiconductor device ensuring the planarity of the base of each interconnection layer and suppressing displacement of the interconnection layer in the process of manufacturing the semiconductor device thereby achieving a high degree of integration.
A semiconductor device in one aspect of the present invention includes a semiconductor substrate, a first interconnection layer, a first interlayer insulating film, a second interconnection layer, and a second interlayer insulating film. The semiconductor substrate has a main surface. The first interconnection layer is formed on the semiconductor substrate. The first interlayer insulating film is formed on the semiconductor substrate to cover the first interconnection layer. The second interconnection layer is formed on the first interlayer insulating film. The second interlayer insulating film is formed on the first interlayer insulating film to cover the second interconnection layer. The first interlayer insulating film has a polished top surface, or a film having a polished top surface is laminated on the first interlayer insulating film.
Since the first interlayer insulating film is polished according to the configuration, the surface of the first interlayer insulating film is planarized over the entire wafer surface in the manufacturing process. Thus, the second interconnection layer that is highly dimensionally precise can easily be formed on the first interlayer insulating film. When the second interlayer insulating film is formed on the first interlayer insulating film to cover the second interconnection layer, heat from the process is applied to the first interlayer insulating film. Since the surface of the first interlayer insulating film is planarized over the entire wafer surface at this time, transformation of the first interlayer insulating film is suppressed compared with the case in which the surface is rough. Thus, displacement of the second interconnection layer causing the second interconnection layer to be moved due to the transformation of the first interlayer insulating film as its base can be suppressed. As a result, a semiconductor device having a higher degree of integration can be obtained.
Preferably, the first interlayer insulating film includes an impurity-doped insulating film that contains prescribed impurities and is reflowed, and the reflowed impurity-doped insulating film has the polished top surface.
In this case, polishing is provided for the impurity-doped insulating film of which roughness of the surface is locally eased by reflow. Therefore, compared with a film of which roughness of the surface is not eased, variation in the degree of polishing in a wafer surface, and variation in the film thickness of the impurity-doped insulating film in the wafer surface can be reduced in polishing the impurity-doped insulating film.
Preferably, the first interlayer insulating film includes an impurity-doped insulating film that contains prescribed impurities and is reflowed and an impurity-non-doped insulating film that is formed on the reflowed impurity-doped insulating film and does not contain prescribed impurities, and the impurity-non-doped insulating film has the polished top surface.
In this case, the impurity-doped insulating film is covered by the impurity-non-doped insulating film. Even if the impurity-doped insulating film is reflowed and transformed by heat in forming the second interlayer insulating film, therefore, the transformation is suppressed. As a result, displacement of the second interconnection layer can be further suppressed.
Preferably, the first interlayer insulating film includes an impurity-non-doped insulating film that does not contain prescribed impurities, and the impurity-non-doped insulating film has the polished top surface.
In this case, the impurity-non-doped insulating film does not contain the prescribed impurities. Therefore, the impurity-non-doped insulating film is not reflowed and transformed by heat in forming the second interlayer insulating film. Thus, the second interconnection layer is not displaced.
More preferably, the first interlayer insulating film includes a first dipped insulating film formed on the semiconductor substrate by the Spin-On-Glass method to fill a space between the first interconnection layers, and the impurity-non-doped insulating film is formed on the first dipped insulating films.
In this case, the first dipped insulating film eases the roughness of the surface of the impurity-non-doped insulating film before it is polished. Thus, variation in the degree of polishing in the wafer surface can be reduced in polishing the impurity-non-doped insulating film.
Preferably, the second interlayer insulating film includes an interconnection coating insulating film that has a thickness allowing fixing and holding of the second interconnection layer and covers the second interconnection layer.
In this case, the second interconnection layer is fixed more strongly on the first interlayer insulating film by the interconnection coating insulating film. Thus, even if the first interlayer insulating film is transformed by heat in a subsequent manufacturing process, displacement of the second interconnection layer can further be suppressed.
Preferably, the second interlayer insulating film includes a second dipped insulating film formed on the first interlayer insulating film by the Spin-On-Glass method to fill a space between the second interconnection layers or to cover the second interconnection layers.
In this case, the second interconnection layer is fixed more strongly on the first interlayer insulating film by the second dipped insulating film. Thus, even if the first interlayer insulating film is transformed by heat in a subsequent manufacturing process, displacement of the second interconnection layer can be suppressed effectively. The roughness of the wafer surface can also be eased by the second dipped insulating film. Thus, the planarity of a film formed on the second dipped insulating film can be ensured easily.
More preferably, the second interlayer insulating film includes an interconnection protecting film formed between the second interconnection layer and the second dipped insulating film.
In this case, diffusion of an impurity such as hydrogen contained in the second dipped insulating film to the second interconnection layer can be prevented.
A semiconductor device in another aspect of the present invention includes a semiconductor substrate, a first interconnection layer, a first interlayer insulating film, a second interconnection layer, and second interlayer insulating film. The semiconductor substrate has a main surface. The first interconnection layer is formed on the semiconductor substrate. The first interlayer insulating film is formed on the semiconductor substrate to cover the first interconnection layer. The second interconnection layer is formed on the first interlayer insulating film. The second interlayer insulating film is formed on the first interlayer insulating film to cover the second interconnection layer. The first interlayer insulating film includes an impurity-doped insulating film that contains prescribed impurities and is reflowed. The second interlayer insulating film has an interconnection coating insulating film that has a thickness allowing fixing and holding of the second interconnection layer and covers the second interconnection layer.
According to the configuration, the surface of the first interlayer insulating film is locally planarized by the impurity-doped insulating film in the manufacturing process. Thus, the second interconnection layer that is highly dimensionally precise can easily be formed on the first interlayer insulating film. The second interconnection layer is fixed more strongly on the first interlayer insulating film by the interconnection coating insulating film. Thus, even if the impurity-doped insulating film is reflowed and transformed by heat in a sequent manufacturing process, displacement of the second interconnection layer causing the second interconnection layer to be moved due to the transformation of the impurity-doped insulating film can be suppressed. As a result, a semiconductor device having a higher degree of integration can be obtained.
Preferably, the interconnection coating insulating film has a thickness of at least the thickness of the second interconnection layer.
In this case, the second interconnection layer is fixed more reliably on the first interlayer insulating film by the interconnection coating insulating film. Thus, displacement of the second interconnection layer can be suppressed more reliably.
Preferably, the second interlayer insulating film is polished or reflowed.
In this case, a pattern that is highly dimensionally precise can easily be formed on the second interlayer insulating film.
Preferably, the interconnection coating insulating film includes a third dipped insulating film formed by the Spin-On-Glass method to fill a space between the second interconnection layers or to cover the second interconnection layers.
In this case, the roughness of the wafer surface is eased by the third dipped insulating film, and thereafter the planarity of a film formed on the third dipped insulating film can easily be ensured.
More preferably, the second interlayer insulating film includes an interconnection protecting film formed between the second interconnection layer and the third dipped insulating film.
In this case, diffusion of an impurity such as hydrogen contained in the third dipped insulating film to the second interconnection layer can be prevented.
More preferably, an insulating film that does not contain prescribed impurities is formed on the top surface or the bottom surface of the impurity-doped insulating film.
In this case, diffusion of the prescribed impurities contained in the impurity-doped insulating film upward or downward of the impurity-doped insulating film can be prevented by the insulating film.
More preferably, the first interlayer insulating film includes a substrate coating insulating film covering the semiconductor substrate.
In this case, diffusion of prescribed impurities contained in the impurity-doped insulating film to the semiconductor substrate can be prevented by the substrate coating insulating film.
At least one species of impurities selected from the group of boron, phosphorous and arsenic can be applied as the prescribed impurities.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.